2026 Showcase

Technology Exploration Forum Showcase

The Ethernet Alliance held its Technology Exploration Forum (TEF), “The AI Future: Ethernet,” at the Hyatt Centric in Mountain View, CA on October 7–8, 2026. With AI networking converging on Ethernet, the focus has moved from adoption to evolution — 400 Gb/s per lane signaling, the path from 1.6T to 3.2T Ethernet, IM-DD and coherent optics, and next-generation optical packaging. The NextGenInfra.io team was on the ground to capture thought leader perspectives on what Ethernet needs to scale AI across front-end, scale-out, and scale-up networks.

While you're here, feel free to grab our latest research brief right from this page.

Latest Research Brief

Download Our Latest Report

Data Center Networking in 2026 — Scaling to New Heights

More about this report →

No personal info needed to download

Download the Latest Report

By downloading this report, you agree to our Terms of Use and Privacy Policy.

Subscribe to our newsletter and receive new report updates

The monthly AvidThink infrastructure brief. No spam — unsubscribe anytime.

Analysis by AvidThink

What we learned at TEF 2026

Interviews from the Ethernet Alliance's Mountain View forum agree that AI is no longer just adopting Ethernet but setting its pace, pulling 400G per lane, coherent optics, and scale-up into a two-year cycle.

  1. 1.6T is nearly done; 3.2T is the new target

    The Ethernet Alliance expects 802.3dj to be ratified by OFC, though cost per gigabit is still high, and TEF's focus has moved on to 3.2T. 650 Group calls 400G electrical lanes in 400×8 configurations the key to getting there. Arista sees 200G per lane shipping now and 400G per lane in labs by 2028.

  2. Generations now turn over in two years, not seven

    VIAVI traces the speed cadence from seven years in the telecom era to four with hyperscalers and two with AI. Terahop adds that products must be deployment-ready on day one, at volumes of hundreds of millions of optical units. 650 Group sees ports growing tenfold and Ethernet switching passing $300B this decade on its way to $1T.

  3. At 400G per lane, no single modulation wins

    Broadcom matches PAM6 to passive copper and backplanes and PAM4 to active cables. IEEE 802.3dv, chaired by Synopsys' Kent Lusted, is converging on PAM4 for optics while defining both electrical options. Microsoft wants to avoid PAM6-to-PAM4 gearboxing, and Keysight expects 100–250 GHz measurement work to settle the choice within ten months.

  4. Coherent optics moves inside the data center

    OIF says IM-DD tops out around 2 km at 400G, short of what AI campuses with optical switches need, and is launching a 1600 Coherent-Lite project. Ciena says the question is no longer whether to use coherent but which kind: 1600ZR-class DSPs or lower-power, Ethernet-optimized designs, with IEEE decisions starting in 2027.

  5. Optics heads for scale-up

    Panduit expects optics to grow scale-up domains from 72 GPUs to tens of thousands acting as one. Eliyan proposes smartphone-derived micro-pixel arrays to get past the copper wall. The Ethernet Alliance weighs NPO, CPO, and XPO packaging and tracks retimed, half-retimed, and linear pluggable optics, while CommScope questions whether DSP-less linear optics will hold up at 400G.

  6. Power, fiber, and testing get harder

    Panduit sees liquid cooling and eight-plus network planes multiplying fiber counts, and CommScope answers tight loss budgets with low-loss V-groove and self-cleaning connectors. Teledyne shows UEC for scale-out and UALink for scale-up, with LLR and CBFC lengthening test cycles. The Ethernet Alliance is preparing a special 2027 roadmap on Ethernet for AI.

More about this report →

Highlights from industry thought leaders

Video interviews

650 Group

How 400G Electrical Unlocks $1 Trillion AI Network Market This Decade

  • 400G electrical signaling is the key enabler for 3.2 terabit Ethernet in 400×8 configurations.
  • Ethernet entering scale-up, alongside scale-out and scale-across, pushes switching past $300 billion this decade and toward $1 trillion early next decade.
  • Ports grow from tens of millions to hundreds of millions, demanding an order-of-magnitude jump in manufacturing capacity.
Abstract
Alan Weckel, Founder and Technology Analyst at 650 Group, presents at TEF 2026 on how 400 gig electrical technology enables AI-driven network deployments by unlocking 3.2 terabit speeds through 400 by 8 configurations as Ethernet enters the scale-up space alongside scale-out and scale-across domains. He explains that this evolution will drive the Ethernet switching market beyond $300 billion this decade and exceed one trillion dollars early next decade, requiring an order of magnitude expansion in manufacturing capacity as deployments shift from individual switches to switch racks and from tens of millions to hundreds of millions of ports.
Arista Networks

AI Drives Faster Ethernet Adoption: 200G/Lane Now, 400G/Lane by 2028

  • AI is making each Ethernet generation ramp to high volume much faster than before.
  • 200G-per-lane products begin shipping in Q4 with higher volumes next year, and 400G per lane is expected in lab testing by 2028.
  • The Ethernet Alliance speeds IEEE consensus on 400G-per-lane standards and runs early multi-vendor plugfests for interoperability.
Abstract
Andreas "Andy" Bechtolsheim, Founder and Chief Architect at Arista Networks, explains how AI is driving faster Ethernet adoption cycles, with 200 gigabit per lane products shipping in Q4 and 400 gigabit per lane expected in lab testing by 2028. He highlights the Ethernet Alliance's critical role in accelerating IEEE standards consensus and enabling early multi-vendor plugfest testing to ensure interoperability across the industry.
Broadcom

Solving 100G Signaling: Modulation, Power & Channel Reach Trade-offs

  • Modulation, channel reach, and power together form the hardest problem as lane rates double from 200G to 400G.
  • No single modulation fits every topology — PAM6 suits passive copper and backplanes, PAM4 suits active cables.
  • Long reaches need AEC, ACC, or linear optics, and solving 400G calls for a holistic, industry-wide systems approach.
Abstract
Cathy Liu, SerDes Architect at Broadcom and OIF board member, addresses the challenges of 100-gig signaling, explaining that the combination of modulation, channel reach, and power presents the most significant obstacle, with no single modulation perfectly serving all topologies based on current infrastructure. Liu emphasizes that solving the 400-gig challenge requires a holistic systems approach combining modulation decisions with power and latency considerations, noting that PAM6 works best for passive copper cable backplanes, PAM4 for active cables, and long-reach channels need AEC, ACC, or linear optics, while chip-to-module applications can support both standards depending on vendor resources.
Ciena

Coherent Optics Inside Data Centers

  • Coherent optics is finally moving inside the data center with 1.6 terabit Ethernet.
  • AI shifts priorities from cost-per-bit to power, latency, and loss budgets, with optical circuit switches driving higher loss.
  • The debate is now which coherent — 1600ZR-class DSPs or lower-power, Ethernet-optimized designs — with IEEE decisions starting in 2027.
Abstract
Eric Maniloff, Senior Systems Engineer at Ciena, discusses how coherent optics is finally entering data centers with 1.6 terabit Ethernet, driven by AI workloads that prioritize power, latency, and loss budgets over cost-per-bit. He explains that the industry debate has shifted from whether to adopt coherent optics to which type — high-performance 1600 ZR class DSPs versus custom Ethernet-optimized DSPs designed specifically for data center AI applications.
CommScope

448G per Lane: Power, Loss, and Co-Design

  • Power is the top concern at 400G, and it is unclear whether DSP-less linear optics will still work at that rate.
  • Tight optical loss budgets make low-loss, high-density, reliable fiber connectivity essential, co-designed with racks, power, and networking.
  • CommScope is developing V-groove connectors and fast self-cleaning connector technology for AI networks.
Abstract
Earl Parsons, Director of Data Center Architecture Evolution at CommScope, examines the critical challenges of 400G networks in AI deployments, focusing on power consumption, optical loss budgets, and the necessity of low-loss, high-density fiber connectivity with excellent reliability. He emphasizes that co-design across racks, networking, power, and fiber is essential for AI infrastructure, highlighting CommScope's new V-groove connectors and self-cleaning technology as solutions, while expressing confidence that Ethernet will continue as an innovation platform for future AI networks.
Eliyan

Micro-VCSEL Arrays for AI Scale-Up Networks

  • Copper dominates scale-up networks today but can't meet their growing reach requirements.
  • Micro-pixel arrays pack 200 pixels into a square millimeter, with redundancy that boosts reliability.
  • Reusing smartphone face-recognition components keeps the approach widely available and low cost.
Abstract
Ramin Farjadrad, Co-founder and CEO of Eliyan, presents a micro-pixel array approach, inspired by smartphone face-recognition optics, to break through the copper wall in AI scale-up networks. Packing 200 pixels into a square millimeter at simpler modulation, it delivers high bandwidth with built-in redundancy for reliability, and because the components already ship in consumer phones, it is widely available and low cost.
Ethernet Alliance

Key Take Aways from Ethernet Alliance's Technology Exploration Forum 2026

  • The 1.6 terabit Ethernet specification (802.3dj) is nearly complete and expected to be ratified by OFC.
  • The 1.6T ecosystem is maturing fast with strong test, measurement, and interconnect participation, though cost per gigabit remains high.
  • TEF focused on the path to 3.2 terabit Ethernet, building on 1.6T work with input from hyperscalers and manufacturers.
Abstract
David Rodgers, Chair and President of the Ethernet Alliance, reports from the Technology Exploration Forum in Mountain View on the near-complete 1.6 terabit Ethernet specification (802.3dj) expected to be ratified by OFC, the rapidly evolving ecosystem supporting it, and the forum's focus on pathways to 3.2 terabit Ethernet. He highlights the strong participation from hyperscalers, manufacturers, test and measurement companies, and interconnect vendors, noting that the combination of formal presentations and informal discussions creates a highly productive environment for developing new solutions.
Ethernet Alliance

AI Ethernet Infrastructure: Scaling to 400G and Beyond for Hyperscalers

  • TEF 2026 tackled 400 Gb/s copper and the cabling burden of AI campuses with millions of cables between buildings.
  • Optics options span IM-DD and coherent, packaged as NPO, CPO, or the emerging XPO form factor — with testability a challenge that needs early attention.
  • The Ethernet Alliance is preparing a special 2027 roadmap edition focused on Ethernet for AI.
Abstract
John D'Ambrosia, Chair Emeritus of the Ethernet Alliance, discusses critical developments in Ethernet infrastructure for AI applications, covering challenges from 400 Gbit copper implementations to hyperscale data center connectivity, optical solutions including coherent and IM-DD optics, and various packaging approaches like NPO, CPO, and XPO. The Ethernet Alliance is developing a 2027 roadmap focused on Ethernet for AI that will examine emerging technologies including new fibers, connectors, and signaling innovations to advance the platform's evolution.
HPE

Ethernet Physical Layer Specs: FRO, LRO & LPO Update

  • The Ethernet Alliance tracks three optical families: fully retimed (FRO), linear receive (LRO/RTLR), and linear pluggable (LPO).
  • Specs from IEEE 802.3 and OIF are evolving as the industry shifts from 100G to 200G per lane.
  • Alliance reference tables help the community see which host-side solution each application needs.
Abstract
Jeff Maki, Senior Distinguished Technologist at HPE and treasurer of the Ethernet Alliance board, explains how the Alliance tracks physical layer Ethernet specifications from IEEE 802.3 and OIF, including fully retimed optics (FRO), linear receive optics (LRO/RTLR), and linear pluggable optics (LPO), as the industry moves from 100G to 200G per lane. The Alliance publishes reference tables to keep the community informed on these optical options and the host-side specifications that determine which solution fits where.
Keysight Technologies

AI Ethernet at 448G per Lane: Measurement Science Advances

  • Channel and connector limits make the modulation choice for 400 Gbps the central open question.
  • Keysight is building VNAs, oscilloscopes, and test tools for the 100–250 GHz range, along with tools to characterize dielectric materials.
  • Measurement science will shape modulation decisions over the next ten months, with 800 Gbps signaling already in view.
Abstract
John Calvin, Senior Strategic Planner at Keysight Technologies, discusses the company's role in developing validation and interoperability testing tools for AI industry Ethernet interconnects, particularly addressing challenges in the transition to 400 Gbps driven by channel and connector limitations. He highlights Keysight's development of vector network analyzers, oscilloscopes, and test tools for the 100-250 gigahertz space, emphasizing that measurement science will be critical over the next ten months for optimizing modulation format decisions as the industry advances toward 400 Gbps and 800 Gbps signaling.
Microsoft

Making 400G Optical Networks AI-Ready: Challenges and Solutions

  • Link flaps, modulation issues, and form factors with poor serviceability hold back AI-ready 400G optics.
  • Vendors need stronger screening and quality control so the burden doesn't fall on hyperscalers and customers.
  • Microsoft prefers NRZ or PAM4 for optics, since gearboxing from PAM6 to PAM4 adds interoperability, latency, and power penalties.
Abstract
Adrian Motamedi, Sr. Principal Azure Cloud & AI Architect at Microsoft, examines the requirements for making 400G optical networking AI-ready, highlighting challenges such as link flaps, modulation issues, and the need for better form factors with improved serviceability and fiber management. He advocates for vendors to implement stronger screening and quality control processes, expresses preference for NRZ or PAM4 modulation to avoid gearboxing complications, and emphasizes the importance of streamlined modulation schemes across infrastructure to prevent interoperability issues, latency increases, and power impacts.
OIF

AI Data Centers Need 400G Coherent Optics Beyond 2Km

  • At 400G, IM-DD optics max out around 2 km — short of what hyperscale AI campuses need.
  • Coherent optics are likely the only viable option at 2 km and beyond, with room for added loss from connectors and optical switches.
  • OIF's new 1600 Coherent-Lite project and IEEE's planned coherent work call for close coordination to avoid duplication.
Abstract
Tom Issenhuth, MA&E Co-Chair for Physical & Link Layer at OIF, explains why AI infrastructure is pushing coherent optics inside the data center at 400G: IM-DD solutions top out around 2 kilometers, while hyperscale campuses now need longer reaches with extra loss from connectors and optical switches. He discusses OIF's coherent ZR work and its new 1600 Coherent-Lite project for shorter reaches, and calls for close coordination between OIF and IEEE to advance coherent optics for AI data centers.
Panduit

Power, Cooling & Fiber Optic Challenges

  • Power constraints are pushing AI systems from air to liquid cooling.
  • Higher data rates and multi-plane architectures of eight planes or more demand far more fiber infrastructure.
  • Panduit focuses on foolproof, future-proof, and faster-to-deploy solutions to speed cloud providers' time to revenue.
Abstract
Bob Wagner, Senior Business Development Manager at Panduit, discusses how AI systems are driving major changes in data center infrastructure, including the shift from air to liquid cooling due to power constraints and the need for significantly more fiber optic infrastructure to support higher data rates and increasingly complex multi-plane architectures. He explains Panduit's three-pronged strategy of delivering foolproof solutions with protective features, future-proof installations that avoid premature replacement, and faster deployment times to help cloud vendors accelerate their time to revenue.
Panduit

Optics Will Enable Massive GPU Interconnection

  • Optics in scale-up architectures will be the biggest surprise of the next five years.
  • Growing AI models need low latency and high bandwidth across ever-larger scale-up domains.
  • Ethernet-based optics will take scale-up from 72 to 144, then 500, and eventually tens of thousands of GPUs acting as one.
Abstract
Jose M Castro, Fiber Optical Communication Research Manager at Panduit, discusses how the proliferation of optics in scale-up architectures will enable connectivity for hundreds of thousands of GPUs over the next five years. He explains that as AI models grow requiring low latency and high bandwidth, Ethernet-based optical solutions will be the key enabling technology to expand GPU interconnection from 72 to 144, then to 500, and ultimately to thousands or tens of thousands of GPUs functioning as a single unit.
Synopsys

IEEE 802.3dv: 400G Ethernet Standards for AI & Front-End Networks

  • IEEE 802.3dv is defining 400G-per-lane signaling for backplanes, copper cables, and 500-meter optical reaches.
  • The task force has strong consensus on reusing the existing logic architecture and converging on PAM4 for optics.
  • Defining both PAM4 and PAM6 electrical specs leaves room for linear, half-retimed, co-packaged, and near-packaged designs.
Abstract
Kent Lusted, Distinguished Architect at Synopsys and chair of the IEEE 802.3dv 400 Gig per lane signaling task force, updates progress on Ethernet standards development addressing AI network demands for scale-up, scale-out, and front-end connectivity through copper interconnects, electrical backplanes, copper cables, and 500-meter optical reaches. The working group has achieved industry consensus on reusing existing logic architecture, converging toward PAM4 modulation for optical interconnects, and defining specifications for both PAM4 and PAM6 electrical standards to provide flexibility across various media types and interconnect architectures.
TE Connectivity

Solving 448 Gbps per Lane Challenges

  • AI demand forces bandwidth, density, modulation, and power to be solved at the same time.
  • 448 Gbps per lane, nearly unthinkable two years ago, now has PAM4 and PAM6 prototypes — passive for short reach, active or optical for longer.
  • Data centers will look very different in five years, with new architectures, cooling, and power.
Abstract
Ashika Pandankeril Shaji, Manager System Architect at TE Connectivity, discusses how AI is driving Ethernet evolution in data centers, where increasing demand requires simultaneous solutions for bandwidth, density, modulation, and power, with 448 Gbps now achievable through PAM 4 and PAM 6 modulation depending on reach requirements. She predicts data centers will look dramatically different in five years with new architectures and cooling solutions, emphasizing the critical role of industry collaboration through organizations like the Ethernet Alliance in addressing these complex challenges.
Teledyne

Scaling AI Networks: UEC and UALink

  • Ethernet is evolving through Ultra Ethernet (UEC) and UALink to meet AI workload demands.
  • UEC addresses scale-out, while UALink provides scale-up.
  • CBFC demonstrations show how traffic prioritization shapes future AI network architectures.
Abstract
Garrett Dufrenne, Sales Engineer at Teledyne, discusses how Ethernet is evolving to meet AI workload demands through Ultra Ethernet (UEC) for scale-out and UALink for scale-up. He demonstrates both, along with Credit-Based Flow Control (CBFC), to show how traffic prioritization works and what it means for future network architectures.
Teledyne

New Protocols, Lower Latency & Testing Challenges

  • AI needs more than speed — it demands lossless fabrics and much lower latency.
  • New protocols such as UALink, LLR, and CBFC add complexity to Ethernet designs.
  • Development and test cycles for AI products are longer and more complicated, so testing needs more focus before launch.
Abstract
Craig DuFrenne, Sales Director of the Networks Group at Teledyne, discusses how AI changes Ethernet development and testing. Beyond faster speeds, AI demands lossless fabrics and much lower latency, bringing new protocols such as UALink, LLR, and CBFC into the mix. Companies bringing AI products to market should expect longer, more complex development and test cycles and put more focus on testing before launch.
Terahop

AI's 4 Major Challenges to Ethernet Standards in Data Centers

  • AI generations now turn over in 1–2 years, versus the traditional 4–5 year Ethernet cycle.
  • AI data centers need mature, deployment-ready products immediately, at volumes of hundreds of millions of optical units.
  • Scale-up, scale-out, scale-across, and scale-in requirements add complexity to Ethernet standardization.
Abstract
Rangchen Yu, Vice President of Marketing at Terahop, examines four major challenges AI presents to the Ethernet community: accelerated generational changes (now 1-2 years versus traditional 4-5 year cycles), immediate demand for deployment-ready products, massive volume increases requiring hundreds of millions of optical units across multiple generations, and diverse AI infrastructure requirements spanning scale-up, scale-out, scale-across, and scale-in networking. Yu expresses confidence that the Ethernet community will leverage its decades of experience with open standards in optical networking to successfully address these challenges.
VIAVI

Faster Speeds, Shorter Cycles, Massive Scale

  • The cadence between Ethernet speeds has shrunk from seven years in the telecom era to four with hyperscalers, and now two with AI.
  • AI scale jumps from thousands to millions of connections, requiring dozens of factories and production lines.
  • The ecosystem is positioned to reach 400 gigabit per lane and the gigascale data center era despite the compressed timelines.
Abstract
Paul Brooks, Product Line Manager at VIAVI, discusses how AI is accelerating networking infrastructure demands at the Ethernet Alliance TEF 2026 event, with development cycles compressed from seven years to just two years and scale expanding from thousands to millions of connections requiring massive manufacturing capacity. Brooks expresses confidence that the industry ecosystem is well-positioned to meet these challenges and successfully transition to the gigascale data center era despite the compressed timelines and technical hurdles of advancing to 400 gigabit per lane technology.
Reader feedback on Data Center Networking in 2026 — Scaling to New Heights: "Appreciate the broad coverage and unique insights." "Up, Out, Across, and Away we go." Download our latest report and send us your feedback!
Download the Latest Report

By downloading this report, you agree to our Terms of Use and Privacy Policy.

Continue exploring

More executive showcases across next-gen infrastructure.

2025

2025 OCP Global Summit

Exclusive videos from thought leaders covering data center networking (scale-up, scale-out, scale-across), photonics, liquid cooling, SONiC

20 video interviews
2026

2026 AI Infra Summit

Executives at AI Infra Summit 2026 in Santa Clara discuss full-stack AI infrastructure — chips, interconnects, networking, memory, storage, power, and the data centers behind AI training and inference

30 video interviews
2026

2026 Data Center Networking

Infrastructure leaders discuss data center networking and impact of AI/GenAI. Topics: InfiniBand, UEC, NVLink, UALink, ESUN

25 video interviews
Browse all topics →